Jasper Design Automation

Jasper Design Automation, founded as Tempus Fugit in 1999 by Vigyan Singhal and Joe Higgens, established itself as a key player in the electronic design automation (EDA) sector before its acquisition by Cadence Design Systems in June 2014 for approximately $170 million. The company specialized in formal verification, a critical process in the design of complex semiconductors and systems-on-chip (SoCs) that uses mathematical methods to ensure design correctness. This focus was pivotal in an industry where verification accounts for a significant portion of chip development costs.

Under the leadership of President and CEO Kathryn Kranen, who joined in 2003, Jasper transitioned from a niche technology provider to a mainstream solution for design verification. Kranen, an electrical engineer with extensive experience at companies like Rockwell International, Daisy Systems, and Verisity, guided the company to profitability and significant growth. A key strategic milestone was the 2004 merger with Safelogic, a Swedish EDA company, which expanded Jasper's capabilities and market presence.

The company’s core business revolved around its flagship product, the JasperGold Formal Verification Platform. This platform provided a suite of software tools, or "Verification Apps," that enabled engineers to detect and debug design flaws early in the development cycle, long before the costly manufacturing phase. The technology was designed to handle highly complex verification challenges that traditional simulation-based methods struggled with. Its client base included leading semiconductor, systems, and intellectual property (IP) companies in the wireless, consumer, computing, and networking industries. Revenue was generated through a value-based pricing model, selling licenses for its software applications and providing specialized consulting and support services to ensure customer success.

The acquisition by Cadence was a strategic move to integrate Jasper's leading formal analysis technology into Cadence's broader System Development Suite. This combination aimed to create a comprehensive verification solution, merging Jasper's formal techniques with Cadence's strengths in simulation, emulation, and debug analysis. The Jasper team, including Kathryn Kranen, was integrated into Cadence's System & Verification Group following the acquisition.

Keywords: formal verification, electronic design automation, semiconductor design, system-on-chip, RTL verification, intellectual property reuse, JasperGold, assertion-based verification, Cadence, Kathryn Kranen